The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2008

Filed:

May. 03, 2007
Applicants:

Paul J. Aube, Charlotte, VT (US);

Normand Cote, Quebec, CA;

Roger G. Gamache, Jr., Essex Junction, VT (US);

David L. Gardell, Fairfax, VT (US);

Paul M. Gaschke, Wappingers Falls, NY (US);

Marc D. Knox, Hinesburg, VT (US);

Denis D. Turcotte, Quebec, CA;

Inventors:

Paul J. Aube, Charlotte, VT (US);

Normand Cote, Quebec, CA;

Roger G. Gamache, Jr., Essex Junction, VT (US);

David L. Gardell, Fairfax, VT (US);

Paul M. Gaschke, Wappingers Falls, NY (US);

Marc D. Knox, Hinesburg, VT (US);

Denis D. Turcotte, Quebec, CA;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method, system and apparatus for testing an integrated circuit chip. The system including: means for forming a liquid polyalphaolefine layer on a bottom surface of the integrated circuit chip, a top surface of the integrated circuit chip having and a bottom surface not having signal and power pads; means for placing a surface of a heat sink into physical contact with the bottom surface of the polyalphaolefine layer; means for electrically coupling the integrated circuit chip to a tester; means for electrically testing the integrated circuit chip; means for electrically de-coupling the integrated circuit chip from the tester; means for removing the heat sink from contact with the polyalphaolefine layer, all or a portion of the polyalphaolefine layer remaining on the bottom surface of the integrated circuit chip; and means for removing the polyalphaolefine layer from the bottom surface of the integrated circuit chip.


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