The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7331026 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 12, 2008

Filed:

Oct. 12, 2004
Applicant:

Hemanth Sampath, Pittsburgh, PA (US);

Inventor:

Hemanth Sampath, Pittsburgh, PA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system for generating a layout of an integrated circuit is disclosed. The system includes at least one processing unit for executing computer programs, a graphical-user-interface for viewing representations of the integrated circuit on a display and observing the layout of the integrated circuit, and a memory for storing databases of the integrated circuit. The system further includes means for retrieving locations of a plurality of devices from a schematic of the integrated circuit, means for retrieving user-specified placement constraints, and means for placing the devices in accordance with the locations and the user-specified placement constraints.


Find Patent Forward Citations

Sampath, Hemanth. (2008). Method and system for generating an initial layout of an integrated circuit (U.S. Patent No. 7331026). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7331026

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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