The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2008

Filed:

Jun. 09, 2005
Applicants:

Hideaki Saito, Tokyo, JP;

Yasuhiko Hagihara, Tokyo, JP;

Muneo Fukaishi, Tokyo, JP;

Masayuki Mizuno, Tokyo, JP;

Hiroaki Ikeda, Tokyo, JP;

Kayoko Shibata, Tokyo, JP;

Inventors:

Hideaki Saito, Tokyo, JP;

Yasuhiko Hagihara, Tokyo, JP;

Muneo Fukaishi, Tokyo, JP;

Masayuki Mizuno, Tokyo, JP;

Hiroaki Ikeda, Tokyo, JP;

Kayoko Shibata, Tokyo, JP;

Assignees:

NEC Corporation, Tokyo, JP;

Elpida Memory Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 8/12 (2006.01); G11C 8/10 (2006.01); G11C 7/10 (2006.01); G11C 8/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.


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