The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2008

Filed:

Jun. 21, 2005
Applicants:

Wei-chung Lo, Junghe, TW;

Hsin-chien Huang, Hsinchu, TW;

Ming LU, Taipei, TW;

Inventors:

Wei-Chung Lo, Junghe, TW;

Hsin-Chien Huang, Hsinchu, TW;

Ming Lu, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/44 (2006.01); H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is provided for forming wafer level package that incorporates dual compliant layers and a metal cap layer on top of I/O pads. The wafer level package includes a plurality of metal cap layers formed on top of a plurality of I/O pads to function as stress buffering and avoiding sharp corners in metal traces formed on top of the metal cap layers. A first compliant layer and a second compliant layer are formed under the metal trace to provide the necessary standoff and to accommodate differences in coefficients of thermal expansion of the various materials on an IC die. The wafer level package is particularly suitable for copper devices or in devices wherein copper lines are used.


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