The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2008

Filed:

Jun. 22, 2004
Applicants:

Albert Z. H. Wang, Santa Clara, CA (US);

Chen H. Tsay, San Jose, CA (US);

Peter Deane, Los Altos, CA (US);

Inventors:

Albert Z. H. Wang, Santa Clara, CA (US);

Chen H. Tsay, San Jose, CA (US);

Peter Deane, Los Altos, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H02H 3/00 (2006.01); H01L 29/74 (2006.01); H01L 23/62 (2006.01); H01L 21/332 (2006.01);
U.S. Cl.
CPC ...
Abstract

A two-terminal ESD protection structure formed by an arrangement of five adjacent semiconductor regions (, and) of alternating conductivity type provides protection against both positive and negative ESD voltages. The middle semiconductor region electrically floats. When the two terminals (A and K) of the ESD protection structure are subjected to an ESD voltage, the structure goes into operation by triggering one of its two inherent thyristors (and) into a snap-back mode that provides a low impedance path through the structure for discharging the ESD current.


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