The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2008

Filed:

Nov. 28, 2005
Applicants:

OM P. Agrawal, Los Altos, CA (US);

Ravindar M. Lall, Portland, OR (US);

David L. Rutledge, Portland, OR (US);

Tom Gustafson, Portland, OR (US);

Inventors:

Om P. Agrawal, Los Altos, CA (US);

Ravindar M. Lall, Portland, OR (US);

David L. Rutledge, Portland, OR (US);

Tom Gustafson, Portland, OR (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract

In accordance with an embodiment of the present invention, a programmable logic device includes a memory adapted to store information in the programmable logic device, an input/output circuit adapted to transfer information into or out of the programmable logic device, and an interconnect architecture adapted to route information within the programmable logic device. An interface circuit is provided to couple the memory and the input/output circuit to the interconnect architecture.


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