The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2008
Filed:
Nov. 17, 2005
Robert J. Hillard, Avalon, PA (US);
Robert J. Hillard, Avalon, PA (US);
Solid State Measurements, Inc., Pittsburgh, PA (US);
Abstract
A semiconductor wafer or sample having a substrate of semiconducting material is tested by compressing a dielectric between three electrically conductive contacts and a top surface of the semiconductor wafer or sample substrate. The dielectric has a thickness that permits tunneling current to flow therethrough without damaging the dielectric. A first electrical bias is applied to a pair of adjacent contacts and a second electrical bias, such as ground reference, is applied to the other contact whereupon an inversion layer forms in the semiconductor wafer or sample. A value of a current that flows in the semiconductor wafer or sample substrate and across the dielectric, in the form of a tunneling current, is measured in response to the applied electrical biases. A surface mobility of minority carriers in the semiconductor wafer or sample is determined as a function of the applied electrical biases and the value of the measured current.