The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2008
Filed:
Jun. 17, 2005
Harsaran S. Bhatia, Hopewell Junction, NY (US);
Marie S. Cole, Wappingers Falls, NY (US);
Michael S. Cranmer, Poughkeepsie, NY (US);
Jason Lee Frankel, Beacon, NY (US);
Eric Kline, Clinton Corners, NY (US);
Kenneth A. Papae, Hopewell Junction, NY (US);
Paul R. Walling, White Plains, NY (US);
Harsaran S. Bhatia, Hopewell Junction, NY (US);
Marie S. Cole, Wappingers Falls, NY (US);
Michael S. Cranmer, Poughkeepsie, NY (US);
Jason Lee Frankel, Beacon, NY (US);
Eric Kline, Clinton Corners, NY (US);
Kenneth A. Papae, Hopewell Junction, NY (US);
Paul R. Walling, White Plains, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substrate. The subset substrate has identical internal net lists as the portion of the master substrate. The subset substrate is adapted to accommodate a smaller chip than the master substrate. The master substrate is the largest substrate in the system. The invention also prepares a system of chip packages. The invention selects a master substrate and then selects a subset substrate of the master substrate.