The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7324982 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 29, 2008

Filed:

May. 05, 2004
Applicants:

Aik Koon Loh, Singapore, SG;

Keen Fung Wai, Singapore, SG;

Tiam Hock Tan, Singapore, SG;

Roy H. Williams, Loveland, CO (US);

Inventors:

Aik Koon Loh, Singapore, SG;

Keen Fung Wai, Singapore, SG;

Tiam Hock Tan, Singapore, SG;

Roy H. Williams, Loveland, CO (US);

Assignee:

Agilent Technologies, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/00 (2006.01); G06F 19/00 (2006.01); G06F 11/30 (2006.01); G06F 15/00 (2006.01); G06F 11/00 (2006.01); G06N 5/02 (2006.01); G21C 17/00 (2006.01); G01R 27/28 (2006.01); G01R 31/00 (2006.01); G01R 31/14 (2006.01); G01R 31/38 (2006.01); G01R 31/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus for automatically debugging and optimizing an in-circuit test that is used to test a device under test on an automated tester is presented. The novel test debug and optimization technique extracts expert knowledge contained in a knowledge framework and automates the formulation of a valid stable, and preferably optimized, test for execution on an integrated circuit tester.


Find Patent Forward Citations

Loh, Aik. (2008). Method and apparatus for automated debug and optimization of in-circuit tests (U.S. Patent No. 7324982). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7324982

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