Semiconductor memory devices with open bitline architectures and methods of controlling the bitlines of such semiconductor memory devices

Abstract

Semiconductor memory devices and methods of controlling bitlines of such devices in which bitlines of a memory cell array adjacent to an activated memory cell array are precharged to the same voltage. The semiconductor memory devices may include: a sense amplifier which is connected between a pair of bitlines, consisting of a bitline of a first memory cell array and a bitline of a second memory cell array; a first separation unit which controls the connection of the bitline of the first memory cell array to the sense amplifier in response to a first separation control signal; a second separation unit which controls the connection of the bitline of the second memory cell array to the sense amplifier in response to a second separation control signal; a first precharge unit which precharges the bitline of the first memory cell array to a predetermined voltage in response to a first precharge signal; and a second precharge unit which precharges the bitline of the second memory cell array to the predetermined voltage in response to a second precharge signal, wherein the second separation unit disconnects the bitline of the second memory cell array from the sense amplifier after a sensing operation performed on the first memory cell array, which is activated, is terminated, and the second precharge unit precharges the bitline of the second memory cell array.