The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2008
Filed:
Aug. 02, 2005
Kyoung-woo Lee, Seoul, KR;
Jae-yeol Maeng, Suwon-si, KR;
Jae-hak Kim, Seoul, KR;
Il-whan OH, Seongnam-si, KR;
Hong-jae Shin, Seoul, KR;
Kyoung-woo Lee, Seoul, KR;
Jae-yeol Maeng, Suwon-si, KR;
Jae-hak Kim, Seoul, KR;
Il-whan Oh, Seongnam-si, KR;
Hong-jae Shin, Seoul, KR;
Samsung Electronics Co., Ltd, , KR;
Abstract
Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical formula: (RSiO)x(HSiO)y, wherein x and y satisfy the relationships x+y=1 and 0<x<y<1, and R is selected from C4-C24 alkyl, C4-C24 alkenyl, C4-C24 alkoxy, C8-C24 alkenoxy, substituted C4-C24 hydrocarbon, non-substituted C1-C4 hydrocarbon or substituted C1-C4 hydrocarbon; and, partially etching the filler filling the via and an interlayer dielectric to form a trench, which is connected to the via in the region where the dual damascene interconnections are to be formed. Then, the filler remaining in the via is removed, and the trench and the via are filled with an interconnection material to complete the dual damascene interconnections.