The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2008
Filed:
Mar. 25, 2005
Mehran Sedigh, San Jose, CA (US);
Manuj Rathor, Milpitas, CA (US);
Alain P. Blosse, Belmont, CA (US);
Dutta Saurabh Chowdhury, Farmers Branch, TX (US);
Mehran Sedigh, San Jose, CA (US);
Manuj Rathor, Milpitas, CA (US);
Alain P. Blosse, Belmont, CA (US);
Dutta Saurabh Chowdhury, Farmers Branch, TX (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
In one embodiment, a method of fabricating an integrated circuit includes the steps of: (i) forming composite spacers on sidewalls of a transistor gate, each of the composite spacers comprising a first liner having a stepped portion and a disposable spacer material over the stepped portion; (ii) forming a source/drain region by performing ion implantation through a portion of the first liner over the source/drain region; (iii) replacing the disposable spacer material with a second liner formed over the first liner after forming the source/drain region; (iv) forming a pre-metal dielectric over the second liner; and (v) forming a self-aligned contact through the pre-metal dielectric. Among other advantages, the method allows for an increased contact area for a self-aligned contact.