The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2008

Filed:

Jan. 11, 2005
Applicants:

Masahiro Aoyagi, Tsukuba, JP;

Hiroshi Nakagawa, Tsukuba, JP;

Kazuhiko Tokoro, Tsukuba, JP;

Katsuya Kikuchi, Tsukuba, JP;

Hiroshi Itatani, Yokohama, JP;

Sigemasa Segawa, Yokohama, JP;

Inventors:

Masahiro Aoyagi, Tsukuba, JP;

Hiroshi Nakagawa, Tsukuba, JP;

Kazuhiko Tokoro, Tsukuba, JP;

Katsuya Kikuchi, Tsukuba, JP;

Hiroshi Itatani, Yokohama, JP;

Sigemasa Segawa, Yokohama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A superconducting integrated circuit includes a substrate, a multilayer structure formed on the substrate and composed of a lower superconducting electrode, a tunnel barrier and an upper superconducting electrode sequentially joined together upward in the order mentioned, and an insulating layer perforated to form via holes to get electrical contacts with the lower and upper electrodes. The insulating layer is formed of a high-resolution, photosensitive, solvent-soluble, organic insulating material. The superconducting integrated circuit is produced by a method that includes the steps of depositing the multiplayer on the substrate, applying the insulating material to the front surface of the substrate inclusive of the multiplayer, forming the via holes in the insulating material by the lithographic technique at the prospective positions to get electrical contacts with the upper and lower electrodes, and laying wirings for connecting the upper and lower electrodes through the via holes.


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