The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2008

Filed:

Mar. 30, 2004
Applicants:

David Zimmerman, El Dorado Hills, CA (US);

Edward Weaver, Sunnyvale, CA (US);

Ramasubramanian Rajamani, Cupertino, CA (US);

Inventors:

David Zimmerman, El Dorado Hills, CA (US);

Edward Weaver, Sunnyvale, CA (US);

Ramasubramanian Rajamani, Cupertino, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A buffer logic within a memory module having the capability to carry out a test of another memory module to which it is coupled via a point-to-point bus through autonomously storing and transmitting a test pattern across that point-to-point bus to the other memory module, while further employing another buffer logic that is interposed between the two memory modules to pass on the test pattern, but intercept a signal received from the other memory module during the test and pass on an indication of the receipt of that signal to an analysis device to monitor the test.


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