Memory device and control method therefor

Abstract

An access identification circuit () identifies a first access operation or a second access operation and outputs an identification signal S. During the first access operation, stored data is read out after detecting a column address CADD, a burst address, and updating a word line to newly select memory cells MC. In the second access operation, the memory cells MC connected to the common word line which has been selected are selected by sequentially switching column selector switches. Operating condition information Dx (DAx and/or DBx) used for setting a load condition in a dummy load circuit () and/or setting a pulse width for an equalize signal EQ in an amplification control circuit () is stored in each of first and second storage sections () that are provided for the first and second access operations, respectively. The operating condition information Dx is selected by a selector circuit () in response to the identification signal S and fed to the dummy load circuit () and/or the amplification control circuit (). A suitable operating condition is selected for each of the access operations.