The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2008

Filed:

Dec. 02, 2004
Applicants:

Louis Bernard Bushard, Rochester, MN (US);

Sang Hoo Dhong, Austin, TX (US);

Brian King Flachs, Georgetown, TX (US);

Osamu Takahashi, Round Rock, TX (US);

Michael Brian White, Austin, TX (US);

Inventors:

Louis Bernard Bushard, Rochester, MN (US);

Sang Hoo Dhong, Austin, TX (US);

Brian King Flachs, Georgetown, TX (US);

Osamu Takahashi, Round Rock, TX (US);

Michael Brian White, Austin, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.


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