The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2008
Filed:
Mar. 17, 2006
Yoshio Takazawa, Kodaira, JP;
Toshio Yamada, Koganei, JP;
Shinichi Ozawa, Hachioji, JP;
Takeo Kanai, Kodaira, JP;
Minoru Katoh, Akiruno, JP;
Koudou Yamauchi, Fukuoka, JP;
Toshihiro Araki, Dazaifu, JP;
Yoshio Takazawa, Kodaira, JP;
Toshio Yamada, Koganei, JP;
Shinichi Ozawa, Hachioji, JP;
Takeo Kanai, Kodaira, JP;
Minoru Katoh, Akiruno, JP;
Koudou Yamauchi, Fukuoka, JP;
Toshihiro Araki, Dazaifu, JP;
Renesas Technology Corp., Tokyo, JP;
Hitachi ULSI Systems Co., Ltd., Tokyo, JP;
Abstract
A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.