The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2008
Filed:
Apr. 16, 2004
Chang Seo Park, Singapore, SG;
Byung Jin Cho, Singapore, SG;
Narayanan T. Balasubramanian, Singapore, SG;
Chang Seo Park, Singapore, SG;
Byung Jin Cho, Singapore, SG;
Narayanan T. Balasubramanian, Singapore, SG;
National University of Singapore, Singapore, SG;
Abstract
A method of constructing a dual metal gate CMOS structure that uses an ultra thin aluminum nitride (AIN) buffer layer between the metal gate and gate dielectric during processing for preventing the gate dielectric from being exposed in the metal etching process. After the unwanted gate metal is etched away, the CMOS structure is annealed. During the annealing, the buffer layer is completely consumed through reaction with the metal gate and a new metal alloy is formed, resulting in only a minimal increase in the equivalent oxide thickness. The buffer layer and gate metals play a key role in determining the work functions of the metal/dielectric interface, since the work functions of the original gate metals are modified as a result of the annealing process.