The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2008
Filed:
Oct. 04, 2005
William E. Grose, Plano, TX (US);
Lonnie L. Lambert, Plano, TX (US);
Jeanne Krayer Pitz, Richardson, TX (US);
Toru Tanaka, Plano, TX (US);
William E. Grose, Plano, TX (US);
Lonnie L. Lambert, Plano, TX (US);
Jeanne Krayer Pitz, Richardson, TX (US);
Toru Tanaka, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method and system for testing a device that includes both a digital and analog portion. The digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. A selector input controls each of the plurality of selector devices, which is electrically coupled to a respective one of the memory cells, and is indirectly coupled to one of the plurality of latch devices. A load clock loads a pattern into the plurality of latch devices. A derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices with the assertion of the selector input. A system clock loads the derivative of the pattern into the plurality of latch devices.