The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2007
Filed:
Feb. 26, 2004
Guenter Stenz, Campbell, CA (US);
Srinivasan Dasasathyan, Sunnyvale, CA (US);
Rajat Aggarwal, Sunnyvale, CA (US);
James L. Saunders, Mountain View, CA (US);
Guenter Stenz, Campbell, CA (US);
Srinivasan Dasasathyan, Sunnyvale, CA (US);
Rajat Aggarwal, Sunnyvale, CA (US);
James L. Saunders, Mountain View, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method () of designing a programmable logic device can include the steps of identifying a cost function that penalizes floorplans of a circuit design that do not fit on the programmable logic device () and defining modules having components of a same type (). A set of shapes associated with a module can be determined (). The circuit design can be annealed () to determine a floorplan using the cost function and the set of shapes for the module.