Fabrication of conductive lines interconnecting first conductive gates in nonvolatile memories having second conductive gates provided by conductive gate lines, wherein the adjacent conductive gate lines for the adjacent columns are spaced from each other, and non-volatile memory structures

Abstract

In a nonvolatile memory, the select gates (S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines () interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an dielectric () formed over control gate lines (). Each control gate line provides control gates for one column of the memory cells. The adjacent control gate lines for the adjacent memory columns are spaced from each other. The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates () are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.