The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2007
Filed:
Dec. 10, 2002
Shigeki Hayashida, Nara, JP;
Tatsuya Morioka, Ikoma, JP;
Yoshihiko Tani, Tenri, JP;
Isamu Ohkubo, Kashiba, JP;
Hideo Wada, Nara, JP;
Shigeki Hayashida, Nara, JP;
Tatsuya Morioka, Ikoma, JP;
Yoshihiko Tani, Tenri, JP;
Isamu Ohkubo, Kashiba, JP;
Hideo Wada, Nara, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
A light receiving device includes a silicon substrate, a first P type diffusion layer on the silicon substrate, and a P type semiconductor layer on the P type diffusion layer. On a surface part of the P type semiconductor layer, two N type diffusion layers as light receiving parts, and a second P type diffusion layer between the two N type diffusion layers are provided. On the P type semiconductor layer, an antireflection film structure composed of a first silicon oxide formed by thermal oxidation and a second silicon oxide formed by CVD is provided. A film thickness of the first silicon oxide is set at about 15 nm, thus a defect in a interface between the first silicon oxide and the P type semiconductor layer is prevented. A film thickness of the second silicon oxide is set at about 100 nm, thus a leak current between cathodes is prevented when a power supply voltage is applied for long period of time.