The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2007

Filed:

Jul. 18, 2005
Applicants:

Satoshi Noda, Ome, JP;

Kenji Kozakai, Tachikawa, JP;

Toru Matsushita, Kokubunji, JP;

Yusuke Jono, Higashiyamato, JP;

Inventors:

Satoshi Noda, Ome, JP;

Kenji Kozakai, Tachikawa, JP;

Toru Matsushita, Kokubunji, JP;

Yusuke Jono, Higashiyamato, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the present invention, which is a nonvolatile memory that includes plural electrically erasable and writable nonvolatile memory cells and performs write-and-verify processing in a write operation on the nonvolatile memory cells, includes an ECC determination circuit that counts the number of bits of write error detected in the write-and-verify processing, and outputs the information, and a status register for holding pass/fail information of the write operation and the information about the number of bits of write error outputted from the ECC determination circuit.


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