The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2007

Filed:

Apr. 28, 2005
Applicants:

Hee Kong Phoon, Perak, MY;

Kian Chin Yap, Penang, MY;

Inventors:

Hee Kong Phoon, Perak, MY;

Kian Chin Yap, Penang, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A mask-programmable logic device includes a macrocell having an external input/output port for 'place-and-route' programming by addition of metallization layers. A programmable 'fixed' layer allows the external input/output port to be isolated from the remainder of the macrocell so that it “floats,” allowing signals to be routed through the external input/output port when the macrocell is not in use, to reduce routing blockages. The macrocell also may have at least one internal input/output port, potentially connected to different logic circuits, and a programmable “fixed” layer that can be used to control which internal input/output port is connected to the external input/output port. By thus allowing multiple logic circuits to share a single external input/output port, routing blockages are reduced.


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