The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2007

Filed:

Apr. 01, 2005
Applicants:

Fook-luen Heng, Yorktown Heights, NY (US);

Jin-fuw Lee, Yorktown Heights, NY (US);

Daniel L. Ostapko, Mahopac, NY (US);

Inventors:

Fook-Luen Heng, Yorktown Heights, NY (US);

Jin-Fuw Lee, Yorktown Heights, NY (US);

Daniel L. Ostapko, Mahopac, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit (IC) including at least one combinational logic path. The features in the combinational logic path are self compensating for out-of-focus effects. In particular, field effect transistor (FET) gates may be iso-focally spaced such that the gate (critical dimension) may move with changing focus, but the gate length remains the same. Alternately, logic circuits in a path may self-compensate for focus effects on individual circuits.


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