The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2007
Filed:
Feb. 10, 2005
Anand Haridass, Austin, TX (US);
Andreas Huber, Austin, TX (US);
Erich Klink, Schoenaich, DE;
Jochen Supper, Herrenberg, DE;
Anand Haridass, Austin, TX (US);
Andreas Huber, Austin, TX (US);
Erich Klink, Schoenaich, DE;
Jochen Supper, Herrenberg, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of different known mechanisms and generally results in a noise-map being generated for the integrated circuit. Thereafter, a mapping function is applied to the noise map for each cell to determine a required capacitance for the cells of the integrated circuit. From this required capacitance per cell, the necessary decoupling capacitors may be identified as well as the location for insertion of these decoupling capacitors. In a similar manner, decoupling capacitors may be removed from cells of the integrated circuit based upon the determined required capacitance per cell.