The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2007
Filed:
Mar. 21, 2006
Kai Weber, Boeblingen, DE;
Christian Jacobi, Schoenaich, DE;
Nico Gulden, Unterwirbach, DE;
Viresh Paruthi, Austin, TX (US);
Klaus Keuerleber, Stuttgart, DE;
Kai Weber, Boeblingen, DE;
Christian Jacobi, Schoenaich, DE;
Nico Gulden, Unterwirbach, DE;
Viresh Paruthi, Austin, TX (US);
Klaus Keuerleber, Stuttgart, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by replacing the parts that cannot be formally verified easily. In one form the invention is applied to a logic design including a multiplier circuit. The multiplier is replaced () by pseudo inputs. The input signal values of the multiplier circuit are determined () automatically from a counterexample () delivered () by a functional formal verification system for a modified design where the multiplier is replaced by pseudo signals. The input signal values are combined () with other known inputs to form a test case () file that can be used by a logic simulator to analyse the counterexample () on the unmodified hardware design including the multiplier.