Skew cancellation for source synchronous clock and data signals

Abstract

The skew between a received clock signal and a received data signal that are source synchronous, is accounted for such that stable bit values of the received data signal may be sampled. For programmable skew cancellation, a skew value corresponding to the amount of the skew is determined and programmed into a data storage device. Sampling clock signals of the same frequency but different phases are generated from the clock signal, and one of the sampling clock signals having the desired phase is selected depending on the programmed skew value. Alternatively, for automatic skew cancellation, a phase locked loop compares the received data signal to one of the sampling clock signals to determine the skew value for selecting the sampling clock signal having the desired phase. Stable bit values of the data signal are then sampled with the selected sampling clock signal.