The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2007
Filed:
Apr. 24, 2006
Amit Khanuja, Fremont, CA (US);
Amit Khanuja, Fremont, CA (US);
Virage Logic Corp., Fremont, CA (US);
Abstract
A partitioned source line architecture for reducing leakage and power in a ROM. In one embodiment, a ROM is comprised of a plurality of storage cells organized as an array having M rows and N columns. Each column is associated with a precharged source line that is partitioned into a plurality of source line segments based on the number of row banks of the array. A plurality of local source line decoder circuits corresponding to the row banks are provided for decoding a selected source line segment based on the column address as well as a Bank Select signal generated from the row address of a particular cell. Local pull-down circuitry is provided with each bank for deactivating the selected source line segment upon commencing a memory access operation.