The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2007
Filed:
Aug. 12, 2005
Manabu Kawabe, Hachioji, JP;
Kazuyuki Hori, Tokyo, JP;
Satoshi Tanaka, Kokubunji, JP;
Yukinori Akamine, Kokubunji, JP;
Masumi Kasahara, Takasaki, JP;
Kazuo Watanabe, Takasaki, JP;
Manabu Kawabe, Hachioji, JP;
Kazuyuki Hori, Tokyo, JP;
Satoshi Tanaka, Kokubunji, JP;
Yukinori Akamine, Kokubunji, JP;
Masumi Kasahara, Takasaki, JP;
Kazuo Watanabe, Takasaki, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.