The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2007
Filed:
Nov. 15, 2004
Sunhom Paak, San Jose, CA (US);
David Kuan-yu Liu, Fremont, CA (US);
Anders T. Dejenfelt, Kagerod, SE;
Cyrus Chang, San Jose, CA (US);
Qi Lin, Cupertino, CA (US);
Phillip A. Young, Albuquerque, NM (US);
Sunhom Paak, San Jose, CA (US);
David Kuan-Yu Liu, Fremont, CA (US);
Anders T. Dejenfelt, Kagerod, SE;
Cyrus Chang, San Jose, CA (US);
Qi Lin, Cupertino, CA (US);
Phillip A. Young, Albuquerque, NM (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A nonvolatile EEPROM cell having a double poly arrangement provides stored data without sense amplifiers, thereby reducing power requirements. The EEPROM cell has a floating gate in a first poly layer, and a control gate overlapping the floating gate in a second poly layer. This configuration allows for an area-efficient layout that is easily shrinkable as compared to prior art memory cells. In addition, stacking the control and floating gates results in higher capacitive coupling. The EEPROM cell also includes an access gate, a tunnel capacitor, and at least one inverter. In some embodiments, the EEPROM cell can be advantageously used to configure programmable logic without need for a conloading step.