Method for patterning sub-lithographic features in semiconductor manufacturing

Abstract

A method of forming a gate electrode (') for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer (), for example formed of silicon-rich nitride, is deposited over a polysilicon layer () from which the gate electrode (′) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer () is then formed over the hardmask layer (), and photoresist () is photolithographically patterned to define the pattern of the gate electrode (′), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist () to the BARC layer (). The remaining elements of the BARC layer () are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer () by an anisotropic etch of that layer, using the trimmed BARC elements () as a mask. The hardmask layer elements (′) then mask the etch of the underlying polysilicon layer (), to define the gate electrodes (′), having gate widths that are narrower than the minimum dimension available through photolithography.