The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2007
Filed:
Feb. 04, 2004
Chia-shun Hsiao, Cupertino, CA (US);
Chunchieh Huang, Fremont, CA (US);
Jin-ho Kim, San Jose, CA (US);
Kuei-chang Tsai, Cupertino, CA (US);
Barbara Haselden, Cupertino, CA (US);
Daniel C. Wang, San Jose, CA (US);
Chia-Shun Hsiao, Cupertino, CA (US);
Chunchieh Huang, Fremont, CA (US);
Jin-Ho Kim, San Jose, CA (US);
Kuei-Chang Tsai, Cupertino, CA (US);
Barbara Haselden, Cupertino, CA (US);
Daniel C. Wang, San Jose, CA (US);
ProMOS Technologies Inc., Hsin Chu, TW;
Abstract
Nonvolatile memory wordlines () are formed as sidewall spacers on sidewalls of control gate structures (). Each control gate structure may contain floating and control gates (), or some other elements. Pedestals () are formed adjacent to the control gate structures before the conductive layer () for the wordlines is deposited. The pedestals will facilitate formation of the contact openings () that will be etched in an overlying dielectric () to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.