The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2007
Filed:
Aug. 15, 2003
Tadahiro Ohmi, Swndai-shi, Miyagi-ken 980-0845, JP;
Makoto Imai, Miyagi-ken, JP;
Toshiyuki Nozawa, Miyagi-ken, JP;
Masanori Fujibayashi, Miyagi-Ken, JP;
Koji Kotani, Chiba-ken, JP;
Tadashi Shibata, Tokyo, JP;
Takahisa Nitta, Tokyo, JP;
Tadahiro Ohmi, Swndai-shi, Miyagi-ken 980-0845, JP;
Makoto Imai, Miyagi-ken, JP;
Toshiyuki Nozawa, Miyagi-ken, JP;
Masanori Fujibayashi, Miyagi-Ken, JP;
Koji Kotani, Chiba-ken, JP;
Tadashi Shibata, Tokyo, JP;
Takahisa Nitta, Tokyo, JP;
Other;
Kabushiki Kaisha Ultraclean Technology Research Institute, Tokyo, JP;
I & F, Inc., Tokyo, JP;
Abstract
There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders) for outputting carry data representing this carry, and delay means (memory) for delaying the computation result from the computation circuit by one computation time unit, are provided.