Timing generation circuit and semiconductor test device having the timing generation circuit

Abstract

A timing generation circuit can increase a maximum delay amount without changing the configuration of a timing memory. The timing generation circuit includes: a timing memory (TMM)containing predetermined timing data; a plurality of down countersfor loading the timing data from the TMM and outputting a pulse signal at the timing indicated by the timing data; an address selection circuitfor specifying one or two TMM addresses by switching and outputting corresponding one or plural timing data; a load data switching circuitfor loading the plural timing data to the plural down counters cascaded and outputting one timing pulse signal; and a timing data selection circuitfor selecting one of the pulse signals. The plural timing data are generated by dividing the timing memory into a plurality of memory regions either in a column or row direction.