The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2007

Filed:

Oct. 17, 2005
Applicants:

R. Suryanarayanan Iyer, St. Paul, MN (US);

Sanjeev Tandon, Sunnyvale, CA (US);

Inventors:

R. Suryanarayanan Iyer, St. Paul, MN (US);

Sanjeev Tandon, Sunnyvale, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

Embodiments of methods for fabricating a spacer structure on a semiconductor substrate are provided herein. In one embodiment, a method for fabricating a spacer structure on a semiconductor substrate includes providing a substrate containing a base structure over which the spacer structure is to be formed. The spacer structure may be formed over the base structure by depositing a first layer comprising silicon nitride on the base structure, depositing a second layer comprising a silicon-based dielectric material on the first layer, and depositing a third layer comprising silicon nitride on the second layer. The first, second, and third layers are deposited in a single processing reactor.

Published as:
US2007087575A1; WO2007047019A1; CN1959941A; TW200725753A; US7294581B2; CN100580890C; TWI352393B;

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