The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2007
Filed:
May. 29, 2002
Applicants:
Rahul Saxena, Sunnyvale, CA (US);
Hitesh Rastogi, San Jose, CA (US);
Ashwani Oberai, Milpitas, CA (US);
Inventors:
Rahul Saxena, Sunnyvale, CA (US);
Hitesh Rastogi, San Jose, CA (US);
Ashwani Oberai, Milpitas, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method and system is provided for a multi-level memory. The system includes an internal memory and an external memory. Data packets are received through one or more input ports and initially stored in the internal memory. A control unit determines whether there is congestion of resources within the system and transfers data packets to external memory to ease the congestion. Data packets are eventually transferred from the internal or external memory to one or more output ports.