The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2007
Filed:
Dec. 28, 2005
Tadashi Onodera, Tokyo, JP;
Tadashi Onodera, Tokyo, JP;
Elpida Memory Inc., Tokyo, JP;
Abstract
A delay circuit comprises: N-stage circuits having a first circit to a N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1≦i≦N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.