The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2007

Filed:

Dec. 01, 2004
Applicants:

Masahiko Niwayama, Kyoto, JP;

Kenji Yoneda, Kyoto, JP;

Kazuma Takahashi, Kyoto, JP;

Inventors:

Masahiko Niwayama, Kyoto, JP;

Kenji Yoneda, Kyoto, JP;

Kazuma Takahashi, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating a semiconductor device includes the steps of: forming a semiconductor region of a first conductive type on a semiconductor wafer; forming a gate electrode on the semiconductor region; on the semiconductor region, forming a first insulating film over the whole surface including the upper surface of the gate electrode; by removing the formed first insulating film through etching from the top surface side, forming first sidewalls, covering the side surfaces of the gate electrode, from the first insulating film; and by implanting first impurity ions of a second conductive type to the semiconductor region by using an ion implantation device capable of processing a plurality of semiconductor wafers collectively, forming first impurity diffusion regions on both sides of the gate electrode in the semiconductor region. In the step of forming the first impurity diffusion regions, implantation of the first impurity ions are dividedly performed a plurality of times, and the semiconductor wafer is rotated in its wafer surface for each ion implantation.


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