The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2007

Filed:

Nov. 20, 2003
Applicants:

Sang Hoo Dhong, Austin, TX (US);

Silvia Melitta Mueller, Saarland, DE;

Hwa-joon OH, Austin, TX (US);

Kevin D. Tran, Austin, TX (US);

Inventors:

Sang Hoo Dhong, Austin, TX (US);

Silvia Melitta Mueller, Saarland, DE;

Hwa-Joon Oh, Austin, TX (US);

Kevin D. Tran, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal. Exponent logic, is configured to generate an exponent value, a first incremented exponent value, and a second incremented exponent value. Exponent adjust and rounding logic configured to receive the exponent value, the first incremented exponent value, and the second incremented exponent value. The exponent adjust and rounding logic is further configured to add the inverted leading zero signal to the first incremented exponent value and the second incremented exponent value, thereby producing an exponent output value, a first incremented exponent output value, and a second incremented exponent output value. Either the exponent output value, the first incremented exponent output value, or the second exponent output value are then selected.


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