The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2007
Filed:
Sep. 23, 2004
Bunshi Kuratomi, Kodaira, JP;
Takafumi Nishita, Iruma, JP;
Fukumi Shimizu, Tachikawa, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
For molding semiconductor chips on a wiring substrate matrix with a sealing resin, the wiring substrate matrix is placed on a lower die cavity block of a lower die, and, thereafter, an upper die is brought down, whereby an outer peripheral portion of a cavity of the upper die comes into abutment against an outer peripheral portion of a main surface of the wiring substrate matrix, causing the substrate matrix to be deformed a sufficient extent to prevent resin leakage. Thereafter, block pins provided on the upper die push down the lower die cavity block. Thus, when clamping the wiring substrate matrix using both upper and lower dies, it is possible to suppress or prevent the application of excessive pressure to the wiring substrate matrix and to suppress or prevent deformation or cracking caused by crushing of the wiring substrate matrix. Consequently, the semiconductor device manufacturing yield can be improved.