The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2007

Filed:

Mar. 25, 2004
Applicants:

Hsin-shih Wang, Fremont, CA (US);

Shang-jyh Shieh, Kao-Hsiung Hsien, TW;

Ming-hsin Ku, Kao-Hsiung, TW;

Inventors:

Hsin-Shih Wang, Fremont, CA (US);

Shang-Jyh Shieh, Kao-Hsiung Hsien, TW;

Ming-Hsin Ku, Kao-Hsiung, TW;

Assignee:

Faraday Technology Corp., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for programming a routing layout design through one via layer includes forming a plurality of metal traces on a first routing layer and a second routing layer, and positioning a plurality of vias within a via layer disposed between the first and second routing layers for connecting the metal traces on the first and second routing layers according to a first current route defined by a predetermined circuit layout design to connect a first node and a second node so as to establish a second current route equivalent to the first current route.


Find Patent Forward Citations

Wang, Hsin-Shih. (2007). Method for programming a routing layout design through one via layer (U.S. Patent No. 7287320). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7287320

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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