Method of simplifying a circuit for equivalence checking

Abstract

A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a fixed delay circuit. If the logic circuit is a variable delay circuit, it is converted to a fixed delay circuit by using additional circuitry to obtain a fixed delay circuit. If the fixed delay circuit is a logic circuit that performs multiple cycle computations, it is converted to a logic circuit that performs the same computation in a single cycle. Circuit acceleration includes concatenating multiple copies of the fixed delay circuit. After performing circuit acceleration on all sub-circuits in the fixed delay circuit, a combined accelerated circuit is obtained. Thereafter, redundant flip-flops are identified and removed from the combined accelerated circuit and the combined accelerated circuit is optimized.