The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2007
Filed:
Dec. 13, 2004
Brad W. Simeral, San Francisco, CA (US);
Sean Jeffrey Treichler, Mountain View, CA (US);
David G. Reed, Saratoga, CA (US);
Roman Surgutchik, Santa Clara, CA (US);
Brad W. Simeral, San Francisco, CA (US);
Sean Jeffrey Treichler, Mountain View, CA (US);
David G. Reed, Saratoga, CA (US);
Roman Surgutchik, Santa Clara, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
A system, apparatus, and method are disclosed for increasing the physical memory size accessible to a processor, at least in part, by reclaiming physical address space typically associated with addresses of a restricted linear address space (i.e., addresses that are otherwise unusable by the processor as system memory). In one embodiment, an exemplary memory controller redirects a linear address associated with a range of addresses to access a reclaimed memory hole. The memory controller includes an address translator configured to determine an amount of restricted addresses and to establish a baseline address identified as a first number being a first integer power of 2. The range of addresses can be located at another address identified as a second number being a second integer power of 2. As such, the address translator translates the linear address into a translated address associated with the reclaimed memory hole based on the baseline address.