The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2007

Filed:

Aug. 10, 2002
Applicants:

Pavel Poplevine, Foster City, CA (US);

Annie-li-koow Lum, Milpitas, CA (US);

Hengyang Lin, San Jose, CA (US);

Andrew J. Franklin, Santa Clara, CA (US);

Inventors:

Pavel Poplevine, Foster City, CA (US);

Annie-Li-Koow Lum, Milpitas, CA (US);

Hengyang Lin, San Jose, CA (US);

Andrew J. Franklin, Santa Clara, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a SRAM structure, space and power saving is achieved by providing row and column select lines to select a specific bit cell, and reducing the number of bit lines in the structure used for writing to and reading from the bit cells. The number of bit lines is reduced by sharing bit lines of adjacent bit cells. Furthermore, in order to achieve power saving, the load on the row select lines is reduced by sharing the pass gates between adjacent bit cells that are used to control precharging, reading from and writing to the bit cells.


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