The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2007
Filed:
Sep. 30, 2005
Josef Bock, Munich, DE;
Thomas Meister, Taufkirchen, DE;
Reinhard Stengl, Stadtbergen, DE;
Herbert Schafer, Hohenkirchen-Siegertsbrunn, DE;
Josef Bock, Munich, DE;
Thomas Meister, Taufkirchen, DE;
Reinhard Stengl, Stadtbergen, DE;
Herbert Schafer, Hohenkirchen-Siegertsbrunn, DE;
Infineon Technologies AG, Munich, DE;
Abstract
The invention relates to a method for producing a bipolar semiconductor element, especially a bipolar transistor, and a corresponding bipolar semiconductor component. The inventive method comprises the following steps: a first semiconductor area () of a first conductivity type (p) is provided above a semiconductor substrate (); a connecting area () of the first conductivity type (p<+>) is provided above the semiconductor area (); a first insulating area () is provided above the connecting area (); a window (F) is formed within the first insulating area () and the connecting area () so as to at least partly expose the semiconductor area (); a sidewall spacer () is provided in the window (F) in order to insulate the connecting area (); a second semiconductor area () of the second conductivity type (n+) is provided so as to cover the sidewall spacer () and a portion of the surrounding first insulating area (); the surrounding first insulating area () and the sidewall spacer () are removed in order to form a gap (LS) between the connecting area () and the second semiconductor area (); and the gap (LS) is sealed by means of a second insulating area () while a gaseous atmosphere or a vacuum atmosphere is provided inside the sealed gap (LS).