The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2007

Filed:

Oct. 14, 2004
Applicants:

Lawrence A. Clevenger, La Grangeville, NY (US);

Timothy Joseph Dalton, Ridgefield, CT (US);

Louis C. Hsu, Fishkill, NY (US);

Conal Eugene Murray, Yorktown Heights, NY (US);

Carl Radens, La Grangeville, NY (US);

Kwong-hon Wong, Wappingers Falls, NY (US);

Chih-chao Yang, Beacon, NY (US);

Inventors:

Lawrence A. Clevenger, La Grangeville, NY (US);

Timothy Joseph Dalton, Ridgefield, CT (US);

Louis C. Hsu, Fishkill, NY (US);

Conal Eugene Murray, Yorktown Heights, NY (US);

Carl Radens, La Grangeville, NY (US);

Kwong-Hon Wong, Wappingers Falls, NY (US);

Chih-Chao Yang, Beacon, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.


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