The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2007
Filed:
Mar. 30, 2005
Mariam G. Sadaka, Austin, TX (US);
Alexander L. Barr, Crolles, FR;
Dejan Jovanovic, Austin, TX (US);
Bich-yen Nguyen, Austin, TX (US);
Voon-yew Thean, Austin, TX (US);
Shawn G. Thomas, Gilbert, AZ (US);
Ted R. White, Austin, TX (US);
Mariam G. Sadaka, Austin, TX (US);
Alexander L. Barr, Crolles, FR;
Dejan Jovanovic, Austin, TX (US);
Bich-Yen Nguyen, Austin, TX (US);
Voon-Yew Thean, Austin, TX (US);
Shawn G. Thomas, Gilbert, AZ (US);
Ted R. White, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.