The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2007

Filed:

Apr. 06, 2006
Applicants:

Nandakumar Sampath, Santa Clara, CA (US);

Enrique Musoll, San Jose, CA (US);

Stephen Melvin, San Francisco, CA (US);

Mario Nemirovsky, Saratoga, CA (US);

Inventors:

Nandakumar Sampath, Santa Clara, CA (US);

Enrique Musoll, San Jose, CA (US);

Stephen Melvin, San Francisco, CA (US);

Mario Nemirovsky, Saratoga, CA (US);

Assignee:

MIPS Technologies, Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/56 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and enqueuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.


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