The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2007
Filed:
Oct. 29, 2004
Peter L. Gammel, Millburn, NJ (US);
Isik C. Kizilyalli, Allentown, PA (US);
Marco G. Mastrapasqua, Annandale, NJ (US);
Muhammed Ayman Shibib, Wyomissing, PA (US);
Zhijian Xie, Oak Ridge, NC (US);
Shuming Xu, Schnecksville, PA (US);
Peter L. Gammel, Millburn, NJ (US);
Isik C. Kizilyalli, Allentown, PA (US);
Marco G. Mastrapasqua, Annandale, NJ (US);
Muhammed Ayman Shibib, Wyomissing, PA (US);
Zhijian Xie, Oak Ridge, NC (US);
Shuming Xu, Schnecksville, PA (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
An MOS device is formed including a semiconductor layer of a first conductivity type, and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A drift region is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer and above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the first and second source/drain regions. The MOS device further includes a shielding structure formed on the insulating layer above at least a portion of the drift region. The shielding structure is configured such that an amount of hot carrier injection degradation in the MOS device is controlled as a function of an amount of coverage of the shielding structure over an upper surface of the drift region.